T2316162A Datasheet | Taiwan Memory Technology

FEATURES - Industry-standard x 16 pinouts and timing functions. - Single 5V (±10%) power supply. .. - All device pins are TTL- patible. - 1K-cycle refresh in 16ms. - Refresh modes: RAS only, CAS BEFORE RAS (CBR) and HIDDEN. - Extended data-out (EDO) PAGE MODE access cycle. - BYTE WRITE and BYTE READ access cycles. 1024K x 16 DYNAMIC RAM EDO PAGE MODE GENERAL DESCRIPTION The T2316162A is a randomly accessed solid state memory containing 16,777,216 bits organized in a x16 configuration. The T2316162A has both BYTE WRITE and WORD WRITE access cycles via two CAS pins. It offers Fast Page mode with Extended Data Output. The T2316162A CAS function and timing are determined by the first CAS to transition low and by the last to transition back high. Use only one of the two CAS and leave the other staying high during WRITE will result in a BYTE WRITE. CASL transiting low in a WRITE cycle will write data into the lower byte (DQ0~DQ7), and CASH transiting low will write data into the upper byte (DQ8~DQ15). OPTION TIMING MARKING 45ns -45 50ns -50 60ns -60 PACKAGE 42-pin SOJ J 44/50-pin TSOPII S PIN ASSIGNMENT ( Top View ) VDD 1 2 3 4 5 6 7 8 9 10 11 50 49 48 47 46 45 44 43 42 41 40 Vss DQ15 DQ14 DQ13 DQ12 Vss DQ11 DQ10 DQ9 DQ8 NC VDD DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 NC NC WE RAS NC NC A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 Vss DQ15 DQ14 DQ13 DQ12 Vss DQ11 DQ10 DQ9 DQ8 NC CASL CASH OE A9 A8 A7 A6 A5 A4 Vss DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 NC NC NC WE RAS NC NC A0 A1 A2 A3 VDD 15 16 17 18 19 20 21 22 23 24 25 36 35 34 33 32 31 30 29 28 27 26 NC CASL CASH OE A9 A8 A7 A6 A5 A4 Vss TM Technology Inc. reserves the right P. 1 to change products or specifications without notice. Publication Date: APR. 2002 Revision:E tm TE CH FUNCTIONAL BLOCK DIAGRAM WE CASL CASH CONTROL LOGIC DATA-IN BUFFER DQ0 16 . . DQ15 .. NO.2 CLOCK GENERATOR DATA-OUT BUFFER 10...