TC59YM916BKG32C Overview
TC59YM916BKG24A,32A,32B,40B,32C,40C PIN ASSIGNMENT (TOP VIEW) DQN9 J VDD VDD VDD GND VTERM H GND G VDD F E GND D VDD C SDI GND B DQN14 RQ10 RQ11 CFM CFMN RSRV RSRV RQ4 RQ3 RQ0 GND VTERM DQ15 DQ5 VDD GND DQ4 VDD GND DQ14 VDD GND VDD GND GND GND VDD VDD VDD GND VTERM VTERM GND GND VDD CMD SCK GND GND VDD GND VDD GND VDD GND GND VTERM GND VDD
TC59YM916BKG32C Key Features
- Highest pin bandwidth available
- 4000/3200/2400 Mb/s Octal Data Rate (ODR) Signaling
- Bi-directional differential RSL (DRSL) Flexible read/write bandwidth allocation Minimum pin count
- Programmable on-chip termination Adaptive impedance matching Reduced system cost and routing plexity
- Highest sustained bandwidth per DRAM device
- 8000/6400/4800 MB/s sustained data rate 8 banks: bank-interleaved transactions at full bandwidth Dynamic request schedul
- 2.0/2.5/3.33 ns request packets
- Point-to-point data interconnect for fastest possible flight time
- Support for low-latency, fast-cycle cores
- Low power
TC59YM916BKG32C Applications
- Highest pin bandwidth available − 4000/3200/2400 Mb/s Octal Data Rate (ODR) Signaling − Bi-directional differential RSL (DRSL) Flexible read/write bandwidth all
- Highest sustained bandwidth per DRAM device − − − − −
- 8000/6400/4800 MB/s sustained data rate 8 banks: bank-interleaved transactions at full bandwidth Dynamic request scheduling Early-Read-after-Write support for m
- Low power − − − − − 1.8V VDD Programmable small-swing I/O signaling (DRSL) Low power PLL/DLL design Power Down Self Refresh support Per pin I/O Power Down for n