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TC58NS256DC - TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 256-MBIT CMOS NAND E2PROM

General Description

The TC58NS256 is a single 3.3-V 256-Mbit (276,824,064) bit NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as 528 bytes × 32 pages × 2048 blocks.

Key Features

  • Organization Memory cell array 528 × 64K × 8 Register 528 × 8 Page size 528 bytes Block size (16K + 512) bytes Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read Mode control Serial input/output, Command control Complies with the SmartMediaTM Electrical Specification and Data Format Specification issued by the SSFDC Forum.
  • Power supply VCC = 3.3 V ± 0.3 V Access time Cell array-register 25 µs max Serial Read cycle 50 ns min Operating curren.

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Datasheet Details

Part number TC58NS256DC
Manufacturer Toshiba
File Size 709.64 KB
Description TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 256-MBIT CMOS NAND E2PROM
Datasheet download datasheet TC58NS256DC Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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TC58NS256DC TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 256-MBIT (32M × 8 BITS) CMOS NAND E PROM (32M BYTE SmartMedia DESCRIPTION 2 TM ) The TC58NS256 is a single 3.3-V 256-Mbit (276,824,064) bit NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as 528 bytes × 32 pages × 2048 blocks. The device has a 528-byte static register which allows program and read data to be transferred between the register and the memory cell array in 528-byte increments. The Erase operation is implemented in a single block unit (16 Kbytes + 512 bytes: 528 bytes × 32 pages). The TC58NS256 is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for command inputs.