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TC58NS256BDC Datasheet 256 Mbit CMOS Nand Eprom

Manufacturer: Toshiba

Overview: TC58NS256BDC TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 2 TM 256-MBIT (32M × 8 BITS) CMOS NAND E PROM (32M BYTE.

General Description

) The TC58NS256B is a single 3.3-V 256-Mbit (276,824,064) bit NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as 528 bytes × 32 pages × 2048 blocks.

The device has a 528-byte static register which allows program and read data to be transferred between the register and the memory cell array in 528-byte increments.

The Erase operation is implemented in a single block unit (16 Kbytes + 512 bytes: 528 bytes × 32 pages).

Key Features

  • Organization Memory cell array 528 × 64K × 8 Register 528 × 8 Page size 528 bytes Block size (16K + 512) bytes Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read Mode control Serial input/output, Command control Complies with the SmartMediaTM Electrical Specification and Data Format Specification issued by the SSFDC Forum.
  • Power supply VCC = 3.3 V ± 0.3 V Program/Erase Cycles 1E5 cycle (with ECC) Access time Cell array-register 25.

Similar Datasheet

Brand Logo Part Number Description Manufacturer
Toshiba Semiconductor Logo TC58NS256DC TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 256-MBIT CMOS NAND E2PROM Toshiba Semiconductor

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