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TC74AC00FN - QUAD 2 - INPUT NAND GATE

Download the TC74AC00FN datasheet PDF. This datasheet also covers the TC74AC00F variant, as both devices belong to the same quad 2 - input nand gate family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • High speed: tpd = 3.8 ns (typ. ) at VCC = 5 V.
  • Low power dissipation: ICC = 4 µA (max) at Ta = 25°C.
  • High noise immunity: VNIH = VNIL = 28% VCC (min).
  • Symmetrical output impedance: |IOH| = IOL = 24 mA (min) Capability of driving 50 Ω transmission lines.
  • Balanced propagation delays: tpLH ∼.
  • tpHL.
  • Wide operating voltage range: VCC (opr) = 2 V to 5.5 V.
  • Pin and function compatible with 74F00 Note: xxxFN (JEDEC SOP) is not avai.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TC74AC00F_ToshibaSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number TC74AC00FN
Manufacturer Toshiba
File Size 351.88 KB
Description QUAD 2 - INPUT NAND GATE
Datasheet download datasheet TC74AC00FN Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
TC74AC00F Quad 2-Input NAND Gate Toshiba
TC74AC00FT Quad 2-Input NAND Gate Toshiba
TC74AC00P Quad 2-Input NAND Gate Toshiba
TC74AC02FN Quad 2-Input NOR Gate Toshiba
TC74AC02FT Quad 2-Input NOR Gate Toshiba

Other Datasheets by Toshiba

Part Number Description
TC74AC02F Quad 2-Input NOR Gate
TC74AC02P Quad 2-Input NOR Gate
TC74AC04F HEX INVERTER
TC74AC04P HEX INVERTER
TC74AC05F HEX INVERTER

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
TC74AC00P/F/FN/FT TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74AC00P,TC74AC00F,TC74AC00FN,TC74AC00FT Quad 2-Input NAND Gate The TC74AC00 is an advanced high speed CMOS 2-INPUT NAND GATE fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The internal circuit is composed of 3 stages including buffer output, which provide high noise immunity and stable output. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Features • High speed: tpd = 3.8 ns (typ.