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TC74AC377FW - OCTAL D-TYPE FLIP-FLOP

Download the TC74AC377FW datasheet PDF. This datasheet also covers the TC74AC377P variant, as both devices belong to the same octal d-type flip-flop family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • High speed: fmax = 140 MHz (typ. ) at VCC = 5 V Low power dissipation: ICC = 8 µA (max) at Ta = 25°C High noise immunity: VNIH = VNIL = 28% VCC (min) Symmetrical output impedance: |IOH| = IOL = 24 mA (min) Capability of driving 50 Ω transmission lines. DataSheet4U. com Balanced propagation delays: tpLH ∼ t.
  • pHL Wide operating voltage range: VCC (opr) = 2 to 5.5 V Pin and function compatible with 74F377 e DataShe.
  • Pin.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TC74AC377P_ToshibaSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
TC74AC373FT Octal D-Type Latch Toshiba
TC74AC373FW Octal D-Type Latch Toshiba
TC74AC374FT Octal D-Type Flip-Flop Toshiba
TC74AC374FW OCTAL D-TYPE FLIP-FLOP Toshiba
TC74AC367FN Hex Bus Buffer Toshiba

Other Datasheets by Toshiba

Part Number Description
TC74AC377F Octal D-Type Flip-Flop
TC74AC377P Octal D-Type Flip-Flop
TC74AC373F Octal D-Type Latch
TC74AC373P Octal D-Type Latch
TC74AC374F Octal D-Type Flip-Flop

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.DataSheet4U.com TC74AC377P/F/FW TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74AC377P,TC74AC377F,TC74AC377FW Octal D-Type Flip-Flop Note: The TC74AC377 is an advanced high speed CMOS OCTAL D-TYPE FLIP FLOP fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type flip-flop is controlled by a clock input (CK) and an enable input ( G ) The signal level applied to the D inputs are transferred to Q outputs during the positive going transition of CK. All inputs are equipped with protection circuits against static discharge or transient excess voltage. xxxFW (JEDEC SOP) is not available in Japan.