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TC7MP245FTG - Low-Voltage/Low-Power Octal Bus Transceiver

Download the TC7MP245FTG datasheet PDF. This datasheet also covers the TC7MP245FK variant, as both devices belong to the same low-voltage/low-power octal bus transceiver family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • Weight: VSSOP20-P-0030-0.50 : 0.03 g (typ. ) VQON20-P-0404-0.50 : 0.0145 g (typ. ).
  • Low-voltage operation : VCC = 1.65 to 3.6 V.
  • Low power current consumption : By a new input circuit, power consumption in OE=H is reduced largely. It is most suitable for battery drive products such as personal digital assistant or a cellular phone.
  • Quiescent supply current.
  • High-speed operation.
  • Output current : ICC = 5 μA (max) (VCC=3.6V) : tpd = 3.0 ns( max).

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TC7MP245FK_ToshibaSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number TC7MP245FTG
Manufacturer Toshiba
File Size 303.58 KB
Description Low-Voltage/Low-Power Octal Bus Transceiver
Datasheet download datasheet TC7MP245FTG Datasheet

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Other Datasheets by Toshiba

Part Number Description
TC7MP245FK Low-Voltage/Low-Power Octal Bus Transceiver
TC7MP01FK Low-Voltage Triple Gate
TC7MP3125FK Low Voltage/Low Power 2-Bit X 2 Dual Supply Bus Transceiver
TC7MP3245FTG Low Voltage/Low Power 4-Bit X 2 Dual Supply Bus Transceiver
TC7MP85400FT Octal Bus Buffer

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
TC7MP245FK/FTG TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC7MP245FK, TC7MP245FTG Low-Voltage/Low-Power Octal Bus Transceiver with Bus-hold The TC7MP245 is a high-performance CMOS octal bus transceiver. By a low power consumption circuit, power consumption has been reduced when a bus terminal is disable state (OE=High). The direction of data transmission is determined by the level of the DIR input. The OE input can be used to disable the device so that the busses are effectively isolated. But, bus of a B bus side at floating state is maintained in an appropriate logic level due to a bus hold circuit to a B bus. Moreover, the bus-hold circuit which is added to a B bus is off when OE is low. All inputs are equipped with protection circuits against static discharge.