Datasheet4U Logo Datasheet4U.com

74HC139D - CMOS Digital Integrated Circuits

General Description

2.

The 74HC139D is a high speed CMOS 2-to-4 LINE DECODER/DEMULTIPLEXER fabricated with silicon gate C2MOS technology.

It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation.

Key Features

  • (1) High speed: tpd = 10 ns (typ. ) at VCC = 5 V (2) Low power dissipation: ICC = 4.0 µA (max) at Ta = 25  (3) Balanced propagation delays: tPLH ≈ tPHL (4) Wide operating voltage range: VCC(opr) = 2.0 to 6.0 V 4. Packaging SOIC16 ©2016 Toshiba Corporation 1 Start of comme.

📥 Download Datasheet

Datasheet Details

Part number 74HC139D
Manufacturer Toshiba
File Size 174.66 KB
Description CMOS Digital Integrated Circuits
Datasheet download datasheet 74HC139D Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
74HC139D Dual 2-to-4 line decoder/demultiplexer nexperia
74HC139 Dual 2-Line To 4-Line Decoders/Demultiplexers Texas Instruments
74HC139 Dual 2-to-4 line decoder/demultiplexer NXP
74HC139 Dual 2-to-4 line decoder/demultiplexer nexperia
74HC139-Q100 Dual 2-to-4 line decoder/demultiplexer NXP

Other Datasheets by Toshiba

Part Number Description
74HC132D Quad 2-Input Schmitt NAND Gate
74HC138D 3-to-8 Line Decoder
74HC123D Dual Monostable Multivibrator
74HC125D Quad Bus Buffer
74HC126D Quad Bus Buffer

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CMOS Digital Integrated Circuits Silicon Monolithic 74HC139D 74HC139D 1. Functional Description • Dual 2-to-4 Line Decoder 2. General The 74HC139D is a high speed CMOS 2-to-4 LINE DECODER/DEMULTIPLEXER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The active low enable input can be used for gating or it can be used as a data input for demultiplexing applications. When the enable input is held "H", all four outputs are fixed at a high logic level independent of the other inputs. All inputs are equipped with protection circuits against static discharge or transient excess voltage. 3. Features (1) High speed: tpd = 10 ns (typ.) at VCC = 5 V (2) Low power dissipation: ICC = 4.