DESCRIPTION
● 8-Bit Shift Register/Latch (3-state) 2. General Shift operation is accomplished on the positive going transition of the SCK input. The output register is loaded with the contents of the shift register on the positive going transition of the RCK input. Since RCK and SCK signal are independent, parallel outputs can be held stable during the shift operation. And, since the parallel outputs are 3-state, it can be directly connected to 8-bit bus. This register can be used in serial-to-parallel conversion, data receivers, etc. All inputs are equipped with protection circuits against static discharge or transient excess voltage. 3. FEATURES
(1) High speed: fMAX = 55 MHz (typ.) at VCC = 5 V (2) Low power dissipation: ICC = 4.0 µA (max) at Ta = 25 (3) Balanced propagation delays: tPLH ≈ tPHL (4) Wide operating voltage range: VCC(opr) = 2.0 V to 6.0 V 4. Packaging SOIC16 ©2016 Toshiba Corporation 1 Start of commercial production 2016-02 2016-12-27 Rev.4.0 5. Pin Assignment 6. Marking 7.
Toshiba
