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74HC595D - 8-Bit Shift Register/Latch

General Description

2.

The 74HC595D is a high speed 8-BIT SHIFT REGISTER/LATCH fabricated with silicon gate C2MOS technology.

It achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation.

Key Features

  • (1) High speed: fMAX = 55 MHz (typ. ) at VCC = 5 V (2) Low power dissipation: ICC = 4.0 µA (max) at Ta = 25 (3) Balanced propagation delays: tPLH ≈ tPHL (4) Wide operating voltage range: VCC(opr) = 2.0 V to 6.0 V 4. Packaging SOIC16 ©2016 Toshiba Corporation 1 Start of commercial production 2016-02 2016-12-27 Rev.4.0 5. Pin Assignment 6. Marking 7. IEC Logic Symbol 74HC595D ©2016 Toshiba Corporation 2 2016-12-27 Rev.4.0 8. Truth Table X: Don't care 9. Timing Chart 74HC595D ©2016 Tosh.

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Datasheet Details

Part number 74HC595D
Manufacturer Toshiba
File Size 266.52 KB
Description 8-Bit Shift Register/Latch
Datasheet download datasheet 74HC595D Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CMOS Digital Integrated Circuits Silicon Monolithic 74HC595D 74HC595D 1. Functional Description • 8-Bit Shift Register/Latch (3-state) 2. General The 74HC595D is a high speed 8-BIT SHIFT REGISTER/LATCH fabricated with silicon gate C2MOS technology. It achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The 74HC595D contains an 8-bit static shift register which feeds an 8-bit storage register. Shift operation is accomplished on the positive going transition of the SCK input. The output register is loaded with the contents of the shift register on the positive going transition of the RCK input. Since RCK and SCK signal are independent, parallel outputs can be held stable during the shift operation.