Datasheet4U Logo Datasheet4U.com

74VHC138FT - 3-to-8 Line Decoder

General Description

2.

The 74VHC138FT is an advanced high speed CMOS 3-to-8 DECODER fabricated with silicon gate C2MOS technology.

It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation.

Key Features

  • (1) AEC-Q100 (Rev. H) (Note 1) (2) Wide operating temperature: Topr = -40 to 125  (3) High speed: tpd = 5.7 ns (typ. ) at VCC = 5 V (4) Low power dissipation: ICC = 4.0 µA (max) at Ta = 25  (5) High noise immunity: VNIH = VNIL = 28 % VCC (min) (6) Power down protection is provided on all inputs. (7) Balanced propagation delays: tPLH ≈ tPHL (8) Wide operating voltage range: VCC(opr) = 2.0 V to 5.5 V (9) Pin and function compatible with 74 series(AC/HC/AHC/LV etc. )138 type. Note 1: This device is.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
74VHC138 3 TO 8 LINE DECODER STMicroelectronics
74VHC138 3-to-8 Decoder/Demultiplexer Fairchild Semiconductor
74VHC132 QUAD 2-INPUT SCHMITT NAND GATE STMicroelectronics
74VHC132 Quad 2-Input NAND Schmitt Trigger Fairchild Semiconductor
74VHC132 Quad 2-Input NAND Schmitt Trigger National Semiconductor

Other Datasheets by Toshiba

Part Number Description
74VHC393FT Dual Binary Counter

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CMOS Digital Integrated Circuits Silicon Monolithic 74VHC138FT 74VHC138FT 1. Functional Description • 3-to-8 Line Decoder 2. General The 74VHC138FT is an advanced high speed CMOS 3-to-8 DECODER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. When the device is enabled, 3 Binary Select inputs (A, B and C) determine which one of the outputs ( Y0 - Y7 ) will go low. When enable input G1 is held low or either G2A or G2B is held high, decoding function is inhibited and all outputs go high. G1, G2A , and G2B inputs are provided to ease cascade connection and for use as an address decoder for memory systems. An input protection circuit ensures that 0 to 5.