TC358765XBG
Key Features
- DSI Receiver Configurable 1- up to 4-Data-Lane DSI Link with bi-directional support on Data Lane 0 Maximum bit rate of 800 Mbps/lane Video input data formats: - RGB565 16 bits per pixel - RGB666 18 bits per pixel - RGB666 loosely packed 24 bits per pixel - RGB888 24 bits per pixel. Video frame size: - Up to 1366×768 24-bit/pixel resolution to single-link LVDS display panel - Up to WUXGA resolutions (1920×1200 18-bit pixels) to dual-link LVDS display panel Supports Video Stream packets for video data transmission. Supports generic long packets for accessing the chip’s register set Supports the path for Host to control the on-chip I2C Master
- LVDS FPD Link Transmitter Supports single-link or dual-link Maximum pixel clock frequency of 85 MHz Maximum throughput of 297.5 MBytes/sec for single-link or 595 Mbytes/sec for dual-link Supports display up to 1366×768 24-bit/pixel resolution for single-link, or up to WUXGA (18 bit/pixel) resolutions for dual-link Supports the following pixel formats: - RGB666 18 bits per pixel - RGB888 24 bits per pixe
