TC358772XBG Datasheet | Toshiba

Overview TC358771XBG The TC358771XBG/TC358772XBG Functional Specification adds back light engine to function of TC358775XBG. TC358771XBG/TC358772XBG is the follow-up chip of TC358774XBG/TC358775XBG, which: 1. Is pin patible to TC358774XBG/TC358775XBG 2. Exhibit LVDS Tx block operates at 1.8V @135 MHz to reduce operation power 3. Back light engine controls the back light level automatically with ambient light and adjusts image contents. The primary function of this chip is DSI-to-LVDS Bridge, enabling video streaming output over DSI link to drive LVDS-patible display panels. The chip supports up to 1600x1200 24-bit pixel resolution for single-link LVDS and up to WUXGA (1920x1200 24-bit pixels) resolution for dual-link LVDS. As a secondary function, the chip also supports an I2C Master which is controlled by the DSI link; this may be used as an interface to any other control functions through I2C. P-VFBGA49-0505-0.65-001 Weight: 31 mg (Typ.) P-VFBGA64-0606-0.65-001 Weight: 47mg (Typ.) Features - DSI Receiver - Configurable 1- up to 4-Data-Lane DSI Link with bi-directional support on Data Lane 0 - Maximum bit rate of 1 Gbps/lane - Video input data formats: - RGB565 16 bits per pixel - RGB666 18 bits per pixel - RGB666 loosely packed 24 bits per pixel - RGB888 24 bits per pixel - Video frame size: - Up to 1600×1200 24-bit/pixel resolution to single-link LVDS display panel, limited by 135 MHz LVDS speed - Up to WUXGA resolutions (1920×1200 24-bit pixels) to dual-link LVDS display panel, limited by 4 Gbps DSI link speed - Supports Video Stream packets for video data transmission. - Supports generic long packets for accessing the chip's register set - Supports the path for Host to control the on-chip I2C Master - LVDS FPD Link Transmitter - Supports single-link or dual-link - Maximum pixel clock frequency of 135 MHz. - Supports display up to 1600×1200 24-bit/pixel resolution for single-link, or up to 1920×1200 24-bit resolutions for dual-link -...