TC358775XBG Datasheet | Toshiba

Overview TC358774XBG The TC358774XBG/TC358775XBG Functional Specification defines operation of the DSISM to LVDS low power chip (or more abbreviated, TC358775XBG chip). TC358775XBG is the follow-up chip of TC358764XBG/ TC358765XBG, which: 1. Is pin patible to TC358764XBG/TC358765XBG P-VFBGA49-0505-0.65-001 Weight: 39 mg (Typ.) 2. Exhibit LVDS Tx block operates at 1.8V @135 MHz to reduce operation power 3. Update 4-lane DSI Rx max bit rate @ 1 Gbps/lane to support 1920×1200×24 @60fps 4. Add STBY pin with to enable turning on VDDIO power first before other power supplies. The primary function of this chip is DSI-to-LVDS Bridge, enabling P-VFBGA64-0606-0.65-001 Weight: 55 mg (Typ.) video streaming output over DSI link to drive LVDS-patible display panels. The chip supports up to 1600×1200 24-bits per pixel resolution for single-link LVDS and up to WUXGA (1920×1200 24-bits pixels) resolution for dual-link LVDS. As a secondary function, the chip also supports an I2C Master which is controlled by the DSI link; this may be used as an interface to any other control functions through I2C. Features - DSI Receiver - Configurable 1- up to 4-Data-Lane DSI Link with bi-directional support on Data Lane 0 - Maximum bit rate of 1 Gbps/lane - Video input data formats: - RGB565 16-bits per pixel - RGB666 18-bits per pixel - RGB666 loosely packed 24-bits per pixel - RGB888 24-bits per pixel - Video frame size: - Up to 1600×1200 24-bits per pixel resolution to single-link LVDS display panel, limited by 135 MHz LVDS speed - Up to WUXGA resolutions (1920×1200 24-bits pixels) to dual-link LVDS display panel, limited by 4 Gbps DSI link speed - Supports Video Stream packets for video data transmission. - Supports generic long packets for accessing the chip's register set - Supports the path for Host to control the on-chip I2C Master - LVDS FPD Link Transmitter - Supports single-link or dual-link - Maximum pixel clock frequency of 135 MHz. - Maximum pixel clock...