TC58BYG2S0HBAI4 Datasheet | Toshiba

TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 4 GBIT (512M × 8 BIT) CMOS NAND E2PROM DESCRIPTION The TC58BYG2S0HBAI4 is a single 1.8V 4 Gbit (4,429,185,024 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (4096 + 128) bytes × 64 pages × 2048blocks. The device has a 4224-byte static register which allows program and read data to be transferred between the register and the memory cell array in 4224-bytes increments. The Erase operation is implemented in a single block unit (256 Kbytes + 8 Kbytes: 4224 bytes × 64 pages). The TC58BYG2S0HBAI4 is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for mand inputs. The Erase and Program operations are automatically executed making the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and other systems which require high-density non-volatile memory data storage. The TC58BYG2S0HBAI4 has ECC logic on the chip and 8bit read errors for each 528Bytes can be corrected internally. Features - Organization Memory cell array Register Page size Block size x8 4224 × 128K × 8 4224 × 8 4224 bytes (256K + 8K) bytes - Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy, Multi Page Read, Multi Page Program, Multi Block Erase, ECC Status Read - Mode control Serial input/output mand control - Number of valid blocks Min 2008 blocks Max 2048 blocks - Power supply VCC = 1.7V to 1.95V - Access time Cell array to register 55 µs typ. (Single Page Read) / 90µs typ. (Multi Page Read) Serial Read Cycle 25 ns min (CL=30p F) - Program/Erase time Auto Page Program Auto Block Erase 340 µs/page typ. 3.5 ms/block typ. - Operating current Read (25 ns cycle) Program (avg.) Erase (avg.) Standby 30 m A max. 30 m A max 30 m A max 50 µA max - Package P-TFBGA63-0911-0.80CZ (Weight: 0.15 g typ.) - 8bit ECC for each...