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TC58NVG2S0HBAI6 - 4G-BIT (512M x 8 BIT) CMOS NAND E2PROM

General Description

The TC58NVG2S0HBAI6 is a single 3.3V 4 Gbit (4,563,402,752 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (4096 + 256) bytes × 64 pages × 2048blocks.

Key Features

  • Organization x8 Memory cell array 4352 × 128K × 8 Register 4352 × 8 Page size 4352 bytes Block size (256K + 16K) bytes.
  • Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy, Multi Page Program, Multi Block Erase, Multi Page Copy, Multi Page Read.
  • Mode control Serial input/output Command control.
  • Number of valid blocks Min 2008 blocks Max 2048 blocks.
  • Power supply VCC = 2.7V to 3.6V.
  • Access time Cell ar.

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Datasheet Details

Part number TC58NVG2S0HBAI6
Manufacturer Toshiba
File Size 489.78 KB
Description 4G-BIT (512M x 8 BIT) CMOS NAND E2PROM
Datasheet download datasheet TC58NVG2S0HBAI6 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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TC58NVG2S0HBAI6 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 4 GBIT (512M × 8 BIT) CMOS NAND E2PROM DESCRIPTION The TC58NVG2S0HBAI6 is a single 3.3V 4 Gbit (4,563,402,752 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (4096 + 256) bytes × 64 pages × 2048blocks. The device has two 4352-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 4352-byte increments. The Erase operation is implemented in a single block unit (256 Kbytes + 16 Kbytes: 4352 bytes × 64 pages). The TC58NVG2S0HBAI6 is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for command inputs.