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TC74HC109AF Datasheet Dual J-k Flip-flop

Manufacturer: Toshiba

Overview: TC74HC109AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC109AP, TC74HC109AF Dual J-K Flip-Flop with Preset and Clear The TC74HC109A is a high speed CMOS J- K FLIP FLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. In accordance with the logic levels applied to the J and K inputs, the outputs change state on the positive going transition of the clock pulse. CLR and PR are independent of the clock and are accomplished by a low logic level on the corresponding input. All inputs are equipped with protection circuits against static discharge or transient excess voltage.

This datasheet includes multiple variants, all published together in a single manufacturer document.

Key Features

  • High speed: fmax = 63 MHz (typ. ) at VCC = 5 V.
  • Low power dissipation: ICC = 2 μA (max) at Ta = 25°C.
  • High noise immunity: VNIH = VNIL = 28% VCC (min).
  • Output drive capability: 10 LSTTL loads.
  • Symmetrical output impedance: |IOH| = IOL = 4 mA (min).
  • Balanced p.

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