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TC74HC109AFN - DUAL J-K FLIP-FLOP

Download the TC74HC109AFN datasheet PDF. This datasheet also covers the TC74HC109 variant, as both devices belong to the same dual j-k flip-flop family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • High speed: fmax = 63 MHz (typ. ) at VCC = 5 V.
  • Low power dissipation: ICC = 2 μA (max) at Ta = 25°C.
  • High noise immunity: VNIH = VNIL = 28% VCC (min).
  • Output drive capability: 10 LSTTL loads.
  • Symmetrical output impedance: |IOH| = IOL = 4 mA (min).
  • Balanced p.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TC74HC109_Toshiba.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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Other Datasheets by Toshiba

Part Number Description
TC74HC109AF Dual J-K Flip-Flop
TC74HC109AP Dual J-K Flip-Flop
TC74HC107AF Dual J-K Flip-Flop
TC74HC107AFN DUAL J-K FLIP-FLOP
TC74HC107AP Dual J-K Flip-Flop

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
TC74HC109AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC109AP, TC74HC109AF Dual J-K Flip-Flop with Preset and Clear The TC74HC109A is a high speed CMOS J- K FLIP FLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. In accordance with the logic levels applied to the J and K inputs, the outputs change state on the positive going transition of the clock pulse. CLR and PR are independent of the clock and are accomplished by a low logic level on the corresponding input. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Features • High speed: fmax = 63 MHz (typ.