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TC74HC173AF - Quad D-Type Register

Download the TC74HC173AF datasheet PDF. This datasheet also covers the TC74HC173AP variant, as both devices belong to the same quad d-type register family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • High speed: fmax = 47 MHz (typ. ) at VCC = 5 V.
  • Low power dissipation: ICC = 4 μA (max) at Ta = 25°C.
  • High noise immunity: VNIH = VNIL = 28% VCC (min).
  • Output drive capability: 15 LSTTL loads.
  • Symmetrical output impedance: |IOH| = IOL = 6 mA (min).
  • Balanced propagation delays: tpLH ∼.
  • tpHL.
  • Wide operating voltage range: VCC (opr) = 2 to 6 V.
  • Pin and function compatible with 74LS173 Pin Assignment TC74HC173AP TC74HC.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TC74HC173AP-Toshiba.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
TC74HC173AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC173AP, TC74HC173AF Quad D-Type Register (3-state) The TC74HC173A is a high speed CMOS D-TYPE REGISTER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. It consists a 4-bit register consisting of D-type flip-flops and 3-state buffers. The four flip-flops are controlled by a common clock input (CK) and a common clear input (CLR). Signals applied to the data inputs (D1 to D4) are stored in the respective flip-flops on the positive going transition of CK when clock control inputs (G1, G2) are held low. The clear function is asynchronous to CK and active on a high level.