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TC74HC245AF - Octal Bus Transceiver

Download the TC74HC245AF datasheet PDF. This datasheet also covers the TC74HC245 variant, as both devices belong to the same octal bus transceiver family and are provided as variant models within a single manufacturer datasheet.

General Description

2.

The TC74HC245A, TC74HC640A are high speed CMOS OCTAL BUS TRANSCEIVERs fabricated with silicon gate C2MOS technology.

Key Features

  • (Note) (1) High speed: tpd = 10 ns (typ. ) at VCC = 5.0 V (2) Low power dissipation: ICC = 4.0 µA (max) at Ta = 25.
  • (3) High noise immunity: VNIH = VNIL = 28 % VCC (min) (4) Output drive capability: 15 LSTTL loads (5) Output current: |IOH|/IOL = 6 mA (min) (VCC = 4.5 V) (6) Balanced propagation delays: tPLH ≈ tPHL (7) Wide operating voltage range: VCC(opr) = 2 V to 6 V (8) Pin and function compatible with 74LS245/640. Note: Do not apply a signal to any bus pins when it is in the output mode.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TC74HC245_Toshiba.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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Other Datasheets by Toshiba

Part Number Description
TC74HC245AP Octal Bus Transceiver
TC74HC240AF Octal Bus Buffer
TC74HC240AP Octal Bus Buffer
TC74HC241AF Octal Bus Buffer
TC74HC241AP Octal Bus Buffer

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
TC74HC245AP,TC74HC245AF,TC74HC640AP,TC74HC640AF CMOS Digital Integrated Circuits Silicon Monolithic TC74HC245AP,TC74HC245AF,TC74HC640AP, TC74HC640AF 1. Functional Description • Octal Bus Transceiver TC74HC245AP/AF:3-State, Non-Inverting TC74HC640AP/AF:3-State, Inverting 2. General The TC74HC245A, TC74HC640A are high speed CMOS OCTAL BUS TRANSCEIVERs fabricated with silicon gate C2MOS technology. They achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. They are intended for two-way asynchronous communication between data busses. The direction of data transmission is determined by the level of the DIR input. The enable input (G) can be used to disable the device so that the busses are effectively isolated.