TC74HC280AP Overview
It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The TC74HC280A is posed of nine data inputs A thru I and odd/even parity outputs Σ ODD and Σ EVEN. The odd parity output is high when an odd number of data inputs are high.
TC74HC280AP Key Features
- High speed: tpd = 22 ns (typ.) at VCC = 5 V
- Low power dissipation: ICC = 4 μA (max) at Ta = 25°C
- High noise immunity: VNIH = VNIL = 28% VCC (min)
- Output drive capability: 10 LSTTL loads
- Symmetrical output impedance: |IOH| = IOL = 4 mA (min)
- Balanced propagation delays: tpLH ∼- tpHL
- Wide operating voltage range: VCC (opr) = 2 to 6 V
- Pin and function patible with 74LS280