Datasheet4U Logo Datasheet4U.com

TC74VCX16835FT - Low-Voltage 18-Bit Universal Bus Driver

Datasheet Summary

Features

  • Low-voltage operation: VCC = 1.8 to 3.6 V.
  • High-speed operation: tpd = 3.3 ns (max) (VCC = 3.0 to 3.6 V) : tpd = 4.2 ns (max) (VCC = 2.3 to 2.7 V) : tpd = 8.4 ns (max) (VCC = 1.8 V).
  • Output current: IOH/IOL = ±24 mA (min) (VCC = 3.0 V) : IOH/IOL = ±18 mA (min) (VCC = 2.3 V) : IOH/IOL = ±6 mA (min) (VCC = 1.8 V).
  • Latch-up performance:.
  • 300 mA.
  • ESD performance: Machine model ≥ ±200 V Human body model ≥ ±2000 V.
  • Package: TSSOP.

📥 Download Datasheet

Datasheet preview – TC74VCX16835FT

Datasheet Details

Part number TC74VCX16835FT
Manufacturer Toshiba
File Size 263.02 KB
Description Low-Voltage 18-Bit Universal Bus Driver
Datasheet download datasheet TC74VCX16835FT Datasheet
Additional preview pages of the TC74VCX16835FT datasheet.

📁 Similar Datasheet

  • TC74VCX2125FK - Low-Voltage Quad Bus Buffer (Toshiba Semiconductor)
  • TC74VCX2573FK - Low-Voltage Octal D-Type Latch (Toshiba Semiconductor)
  • TC74VCX2573FT - Low-Voltage Octal D-Type Latch (Toshiba Semiconductor)
  • TC74VHC03F - Quad 2-Input NAND Gate (Toshiba Semiconductor)
  • TC74VHC03FK - Quad 2-Input NAND Gate (Toshiba Semiconductor)
  • TC74VHC03FN - Quad 2-Input NAND Gate (Toshiba Semiconductor)
  • TC74VHC03FT - Quad 2-Input NAND Gate (Toshiba Semiconductor)
  • TC74VHC9273FK - Octal D-Type Flip-Flop (Toshiba Semiconductor)
  • TC74VHC9273FT - CMOS Digital Integrated Circuit Silicon Monolithic (Toshiba Semiconductor)
  • TC74VHC9273P - Octal D-Type Flip-Flop (Toshiba Semiconductor)
Other Datasheets by Toshiba

Full PDF Text Transcription

Click to expand full text
TC74VCX16835FT TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VCX16835FT Low-Voltage 18-Bit Universal Bus Driver with 3.6-V Tolerant Inputs and Outputs The TC74VCX16835FT is a high-performance CMOS 18-bit universal bus driver. Designed for use in 1.8-V, 2.5-V or 3.3-V systems, it achieves high-speed operation while maintaining the CMOS low power dissipation. It is also designed with overvoltage tolerant inputs and outputs up to 3.6 V. Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is high. When LE is low, the A data is latched if the clock (CK) input is held at a high or low logic level. Weight: 0.25 g (typ.
Published: |