TC74VCX16843FT Datasheet | Toshiba

TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic Low-Voltage 18-Bit D-Type Latch with 3.6-V Tolerant Inputs and Outputs The TC74VCX16843FT is a high-performance CMOS 18-bit D-type latch. Designed for use in 1.8-V, 2.5-V or 3.3-V systems, it achieves high-speed operation while maintaining the CMOS low power dissipation. It is also designed with overvoltage tolerant inputs and outputs up to 3.6 V. The TC74VCX16843FT can be used as two 9-bit latches or one 18-bit latch. The 18 latches are transparent D-type latches. The device has noninverting data (D) inputs and provides true data at its outputs. While the latch-enable (1LE or 2LE) input is high, the Q outputs of the corresponding 9-bit latch follow the D inputs. Weight: 0.25 g (typ.) When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. CLR and PR are independent of the LE and are acplished by setting the appropriate input low. When the OE input is high, the outputs are in a high-impedance state. This device is designed to be used with 3-state memory address drivers, etc. All inputs are equipped with protection circuits against static discharge. Features - Low-voltage operation: VCC = 1.8 to 3.6 V - High-speed operation : tpd = 3.0 ns (max) (VCC = 3.0 to 3.6 V) : tpd = 3.7 ns (max) (VCC = 2.3 to 2.7 V) : tpd = 7.4 ns (max) (VCC = 1.8 V) - Output current: IOH/IOL = ±24 m A (min) (VCC = 3.0 V) : IOH/IOL = ±18 m A (min) (VCC = 2.3 V) : IOH/IOL = ±6 m A (min) (VCC = 1.8 V) - Latch-up performance: - 300 m A - ESD performance: Machine model ≥ ±200 V Human body model ≥ ±2000 V - Package: TSSOP - 3.6-V tolerant function and power-down protection provided on all inputs and outputs Start of mercial production 1997-11 2014-03-01 Pin Assignment (top view) 1CLR 1 1OE 2 1Q1 3 GND 4 1Q2 5 1Q3 6 VCC 7 1Q4 8 1Q5 9 1Q6 10 GND 11 1Q7 12 1Q8 13 1Q9 14 2Q1 15 2Q2 16 2Q3 17 GND 18 2Q4 19 2Q5 20 2Q6 21 VCC 22 2Q7 23 2Q8 24 GND 25...