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TC74VCX2541FK - Low-Voltage Octal Bus Buffer

Download the TC74VCX2541FK datasheet PDF. This datasheet also covers the TC74VCX2541FT variant, as both devices belong to the same low-voltage octal bus buffer family and are provided as variant models within a single manufacturer datasheet.

General Description

2.

The TC74VCX2541FK is a high-performance CMOS octal bus buffer.

Designed for use in 1.8 V, 2.5 V or 3.3 V systems, it achieves high-speed operation while maintaining the CMOS low power dissipation.

Key Features

  • (1) 26 Ω series resistors on outputs. (2) Low-voltage operation: VCC = 1.8 to 3.6 V (3) High-speed operation: tpd = 4.4 ns (max) (VCC = 3.0 to 3.6 V) tpd = 5.6 ns (max) (VCC = 2.3 to 2.7 V) tpd = 9.8 ns (max) (VCC = 1.8 V) (4) Output current: IOH/IOL = ±12 mA (min) (VCC = 3.0 V) IOH/IOL = ±8 mA (min) (VCC = 2.3 V) IOH/IOL = ±4 mA (min) (VCC = 1.8 V) (5) Latch-up performance: -300 mA (6) ESD performance: Human Body Model ≥ ±2000 V (7) 3.6 V tolerant function and power-down protection provided on.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TC74VCX2541FT_ToshibaSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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Other Datasheets by Toshiba

Part Number Description
TC74VCX2541FT Low-Voltage Octal Bus Buffer
TC74VCX2574FK Low-Voltage Octal D-Type Flip-Flop
TC74VCX2574FT Low-Voltage Octal D-Type Flip-Flop
TC74VCX257FK Low-Voltage Quad 2-Channel Multiplexer
TC74VCX257FT Low-Voltage Quad 2-Channel Multiplexer

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CMOS Digital Integrated Circuits Silicon Monolithic TC74VCX2541FK TC74VCX2541FK 1. Functional Description • Low-Voltage Octal Bus Buffer with 3.6-V Tolerant Inputs and Outputs 2. General The TC74VCX2541FK is a high-performance CMOS octal bus buffer. Designed for use in 1.8 V, 2.5 V or 3.3 V systems, it achieves high-speed operation while maintaining the CMOS low power dissipation. It is also designed with overvoltage tolerant inputs and outputs up to 3.6 V. This device is a non-inverting 3-state buffer having two active-low output enables. When either OE1 or OE2 are high, the terminal outputs are in the high-impedance state. This device is designed to be used with 3-state memory address drivers, etc.