Datasheet4U Logo Datasheet4U.com

TC74VHC138FK - 3-to-8 Line Decoder

This page provides the datasheet information for the TC74VHC138FK, a member of the TC74VHC138F 3-to-8 Line Decoder family.

Datasheet Summary

Features

  • High speed: tpd = 5.7 ns (typ. ) at VCC = 5 V.
  • Low power dissipation: ICC = 4 μA (max) at Ta = 25°C.
  • High noise immunity: VNIH = VNIL = 28% VCC (min).
  • Power down protection is provided on all inputs.
  • Balanced propagation delays: tpLH ∼.
  • tpHL.
  • Wide operating voltage range: VCC (opr) = 2 V to 5.5 V.
  • Pin and function compatible with 74ALS138 Weight SOP16-P-300-1.27A VSSOP16-P-0030-0.50 : 0.18 g (typ. ) : 0.02 g (typ. ) © 2019 1 Toshiba Electronic Devic.

📥 Download Datasheet

Datasheet preview – TC74VHC138FK

Datasheet Details

Part number TC74VHC138FK
Manufacturer Toshiba
File Size 332.30 KB
Description 3-to-8 Line Decoder
Datasheet download datasheet TC74VHC138FK Datasheet
Additional preview pages of the TC74VHC138FK datasheet.
Other Datasheets by Toshiba

Full PDF Text Transcription

Click to expand full text
TC74VHC138F/FK TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VHC138F, TC74VHC138FK 3-to-8 Line Decoder The TC74VHC138 is an advanced high speed CMOS 3-to-8 DECODER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. When the device is enabled, 3 Binary Select inputs (A, B and C) determine which one of the outputs ( Y0 - Y7 ) will go low. When enable input G1 is held low or either G2A or G2B is held high, decoding function is inhibited and all outputs go high. G1, G2A , and G2B inputs are provided to ease cascade connection and for use as an address decoder for memory systems. An input protection circuit ensures that 0 to 5.
Published: |