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TC74VHC139FN - DUAL 2-TO-S LINE DECODER

Features

  • High speed: tpd = 5.0 ns (typ. ) at VCC = 5 V.
  • Low power dissipation: ICC = 4 μA (max) at Ta = 25°C.
  • High noise immunity: VNIH = VNIL = 28% VCC (min).
  • Power down protection is provided on all inputs.
  • Balanced propagation delays: tpLH ∼.
  • tpHL.
  • Wide operating voltage range: VCC (opr) = 2 V to 5.5 V.
  • Pin and function compatible with 74ALS139 Pin Assignment Note: xxxFN (JEDEC SOP) is not available in Japan. TC74VHC139F TC74VHC1.

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Datasheet Details

Part number TC74VHC139FN
Manufacturer Toshiba
File Size 220.73 KB
Description DUAL 2-TO-S LINE DECODER
Datasheet download datasheet TC74VHC139FN Datasheet
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TC74VHC139F/FN/FT TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VHC139F,TC74VHC139FN,TC74VHC139FT Dual 2-to-4 Line Decoder The TC74VHC139 is an advanced high speed CMOS 2 to 4 LINE DECODER/DEMULTIPLEXER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The active low enable input can be used for gating or it can be used as a data input for demultiplexing applications. When the enable input is held High, all four outputs are fixed at a high logic level independent of the other inputs. An input protection circuit ensures that 0 to 5.5 V can be applied to the input pins without regard to the supply voltage.
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