TC74VHC367FT Datasheet PDF - Toshiba Hex Bus Buffer Specs

TC74VHC367FT - Hex Bus Buffer

Datasheet Summary

Features

High speed: tpd = 3.8 ns (typ. ) at VCC = 5 V.
Low power dissipation: ICC = 4 μA (max) at Ta = 25°C.
High noise immunity: VNIH = VNIL = 28% VCC (min).
Power down protection is provided on all inputs.
Balanced propagation delays: tpLH ∼.
tpHL.
Wide operating voltage range: VCC (opr) = 2 V to 5.5 V.
Low noise: VOLP = 0.8 V (max).
Pin and function compatible with 74ALS367/368 TC74VHC367FT, TC74VHC368FT TC74VHC367FK,.

Datasheet Details

Part number	TC74VHC367FT
Manufacturer	Toshiba
File Size	245.40 KB
Description	Hex Bus Buffer
Datasheet	TC74VHC367FT Datasheet
Additional preview pages of the TC74VHC367FT datasheet.

📁 Similar Datasheet

TC74VHC03F - Quad 2-Input NAND Gate (Toshiba Semiconductor)

TC74VHC03FK - Quad 2-Input NAND Gate (Toshiba Semiconductor)

TC74VHC03FN - Quad 2-Input NAND Gate (Toshiba Semiconductor)

TC74VHC03FT - Quad 2-Input NAND Gate (Toshiba Semiconductor)

TC74VHC9273FK - Octal D-Type Flip-Flop (Toshiba Semiconductor)

TC74VHC9273FT - CMOS Digital Integrated Circuit Silicon Monolithic (Toshiba Semiconductor)

TC74VHC9273P - Octal D-Type Flip-Flop (Toshiba Semiconductor)

TC74VHC9541FK - Octal Universal Schmitt Buffer (Toshiba Semiconductor)

TC74VHC9541FT - Octal Universal Schmitt Buffer (Toshiba Semiconductor)

TC74VHC9541P - Octal Universal Schmitt Buffer (Toshiba Semiconductor)

Full PDF Text Transcription

Click to expand full text

TC74VHC367,368F/FT/FK TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VHC367F, TC74VHC367FT, TC74VHC367FK TC74VHC368F, TC74VHC368FT, TC74VHC368FK Hex Bus Buffer TC74VHC367F/FT/FK TC74VHC368F/FT/FK Non-Inverted, 3-State Outputs Inverted, 3-State Outputs TC74VHC367F, TC74VHC368F The TC74VHC367 and 368 are advanced high speed CMOS HEX BUS BUFFERs fabricated with silicon gate C2MOS technology. They achieve the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. They contain six buffers; four buffers are controlled by an enable input ( G1 ), and the other two buffers are controlled by another enable input ( G2 ).

Published: Apr 23, 2005 |