TC74VHCT138AFK Overview
It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. When the device is enabled, 3 Binary Select inputs (A, B and C) determine which one of the outputs ( Y0 to Y7 ) will go low. When enable input G1 is held low or either G2A or G2B is held high, decoding function is inhibited and all outputs go high.
TC74VHCT138AFK Key Features
- High speed: tpd = 7.6 ns (typ.) at VCC = 5 V
- Low power dissipation: ICC = 4 μA (max) at Ta = 25°C
- patible with TTL inputs
- Power down protection is provided on all inputs and outputs
- Balanced propagation delays: tpLH ≈ tpHL
- Pin and function patible with the 74 series (74AC/HC/F/ALS/LS etc.) 138 type