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TC74VHCT138AFK - 3-to-8 Line Decoder

This page provides the datasheet information for the TC74VHCT138AFK, a member of the TC74VHCT138AF 3-to-8 Line Decoder family.

Datasheet Summary

Features

  • TC74VHCT138AFK Weight SOP16-P-300-1.27A VSSOP16-P-0030-0.50.
  • High speed: tpd = 7.6 ns (typ. ) at VCC = 5 V.
  • Low power dissipation: ICC = 4 μA (max) at Ta = 25°C.
  • Compatible with TTL inputs: VIL = 0.8 V (max) VIH = 2.0 V (min).
  • Power down protection is provided on all inputs and outputs.
  • Balanced propagation delays: tpLH ≈ tpHL.
  • Pin and function compatible with the 74 series (74AC/HC/F/ALS/LS etc. ) 138 type. : 0.18 g (typ. ) : 0.02 g (typ. ) © 2019 1 Toshiba.

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Datasheet preview – TC74VHCT138AFK

Datasheet Details

Part number TC74VHCT138AFK
Manufacturer Toshiba
File Size 448.93 KB
Description 3-to-8 Line Decoder
Datasheet download datasheet TC74VHCT138AFK Datasheet
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Full PDF Text Transcription

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TC74VHCT138AF/AFK TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VHCT138AF, TC74VHCT138AFK 3-to-8 Line Decoder TC74VHCT138AF The TC74VHCT138 is an advanced high speed CMOS 3-to-8 LINE DECODER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. When the device is enabled, 3 Binary Select inputs (A, B and C) determine which one of the outputs ( Y0 to Y7 ) will go low. When enable input G1 is held low or either G2A or G2B is held high, decoding function is inhibited and all outputs go high. G1, G2A , and G2B inputs are provided to ease cascade connection and for use as an address decoder for memory systems.
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