TC74VHCT573AFT - OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT

Toshiba

Key Features

High speed: tpd = 7.7 ns (typ. ) at VCC = 5 V.
Low power dissipation: ICC = 4 µA (max) at Ta = 25°C.
Compatible with TTL outputs: VIL = 0.8 V (max) VIH = 2.0 V (min).
Power down protection is provided on all inputs and outputs.
Balanced propagation delays: tpLH ∼.
tpHL.
Low noise: VOLP = 1.6 V (max).
Pin and function compatible with the 74 series (74AC/HC/F/ALS/LS etc. ) 573 type. Note: xxxFW (JEDEC SOP) is not available in.

TC74VHCT573AFT octal d-type latch with 3-state output by Toshiba - Datasheet Preview

Datasheet Details

Part number	TC74VHCT573AFT
Manufacturer	Toshiba
File Size	292.29 KB
Description	OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT
Datasheet	TC74VHCT573AFT Datasheet

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Part Number	Description
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TC74VHCT573AF/AFW/AFT TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VHCT573AF,TC74VHCT573AFW,TC74VHCT573AFT Octal D-Type Latch with 3-State Output The TC74VHCT573A is an advanced high speed CMOS OCTAL LATCH with 3-STATE OUTPUT fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type latch is controlled by a latch enable input (LE) and a output enable input ( OE ). When the OE input is high, the eight outputs are in a high impedance state. The input voltage are compatible with TTL output voltage. This device may be used as a level converter for interfacing 3.3 V to 5 V system. Input protection and output circuit ensure that 0 to 5.