TQ2059 Datasheet | TriQuint Semiconductor

Features - Output frequency range: 200 MHz to 350 MHz - One differential PECL output: 600 m V (min) swing - mon-mode voltage: VDD - 1.2 V (max), VDD - 1.6 V (min) - Period-to-period output jitter: 30 ps peak-to-peak (typ) 120 ps peak-to-peak (max) SYSTEM TIMING PRODUCTS VDD NC TEST1 TEST2 NC NC GND 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Control MUX Phase Detector VCO ÷10 ÷2 3 2 NC NC 1 NC 28 NC 27 NC 26 AVDD AGND EVDD PDR2 QN PDR1 GND Q - Reference clock input: 20 MHz to 35 MHz TTL-level crystal oscillator - Self-contained loop filter - Optional 200-ohm pull-down resistors for AC-coupled outputs - +5 V power supply - 28-pin J-lead surface-mount package - Ideal for designs based on DEC Alpha AXP™ processors Tri Quint’s TQ2059 is a high-frequency clock generator. It utilizes a 20 MHz to 35 MHz TTL input to generate a 200 MHz to 350 MHz PECL output. The TQ2059 has a pletely self-contained Phase-Locked Loop (PLL) running at 400 MHz to 700 MHz. This stable PLL allows for a low period-to-period output jitter of 120 ps (max), and enables tight duty-cycle control of 55%to 45% (worst case). The TQ2059 provides optional 200-ohm on-chip pull-down resistors which are useful if the output is AC-coupled to the device being driven. In order to use these resistors, pin 20 (PDR2) should be connected to pin 21 (QN), and pin 23 (PDR1) should be connected to pin 22 (Q). Various test modes on the chip simplify debug and testing of systems by slowing the clock output or by bypassing the PLL. For additional information and latest specifications, see our website: .triquint. Figure 2. Simplified Block Diagram REFCLK (20 MHz to 35 MHz) Phase Detector VCO MUX ÷10 ÷2 TESTIN...