TQ2060 Datasheet | TriQuint Semiconductor

Features - Output frequency range: 350 MHz to 500 MHz - One differential PECL output: 600 m V (min) swing - mon-mode voltage: VDD - 1.2 V (max), VDD - 1.6 V (min) - Period-to-period output jitter: 25 ps peak-to-peak (typ) 70 ps peak-to-peak (max) - Reference clock input: 35 MHz to 50 MHz TTL-level crystal oscillator - Self-contained loop filter - Optional 200-ohm pull-down resistors for AC-coupled outputs - +5 V power supply - 28-pin J-lead surface-mount package - Ideal for designs based on DEC Alpha AXP™ processors 28 NC 27 NC 26 AVDD AGND EVDD PDR2 PDR1 Tri Quint’s TQ2060 is a high-frequency clock generator. It utilizes a 35 MHz to 50 MHz TTL input to generate a 350 MHz to 500 MHz PECL output. The TQ2060 has a pletely self-contained Phase-Locked Loop (PLL) running at 700 MHz to 1000 MHz. This stable PLL allows for a low period-to-period output jitter of 70 ps (max), and enables tight duty cycle control of 55% to 45% (worst case). The TQ2060 provides optional 200 ohm on-chip pull-down resistors which are useful if the output is AC-coupled to the device being driven. In order to use these resistors, pin 20 (PDR2) should be connected to pin 21 (QN), and pin 23 (PDR1) should be connected to pin 22 (Q). Various test modes on the chip simplify debug and testing of systems by slowing the clock output or by bypassing the PLL. For additional information and latest specifications, see our website: .triquint. SYSTEM TIMING PRODUCTS Figure 2. Simplified Block Diagram REFCLK (35MHz to 50 MHz) TESTIN TEST1 Phase Detector VCO MUX ÷ 10 ÷2 MUX QN (350 MHz to Q 500 MHz) Control TEST2 Table 1. Mode Selection Mode 1(Test) 2 (Test) 3 (Test) 4 (Bypass) 5 (Normal TEST1 0 0 1 1 1 TEST2 0 1 0 1 1 TESTIN 1 f TESTCLK “don’t care” f TESTCLK 0...