UR5595 Description
The UTC UR5595 is a linear bus termination regulator designed to meet JEDEC SSTL-2 and SSTL-3 (Stub Series Terminated Logic) specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to the load transients, and can deliver 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. With an...
UR5595 Key Features
- Power regulating with driving and sinking capability
- Low output voltage offset
- No external resistors required
- Low external ponent count
- Linear topology
- Low cost and easy to use
- Thermal shutdown protection
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