UR5596 Description
The UTC UR5596 is a linear bus termination regulator and designed to meet JEDEC SSTL-2(Stub-Series Terminated Logic) specifications for termination of DDR-SDRAM. It also can be used in SSTL-3 or HSTL (High-Speed Transceiver Logic) scheme. The device contains a high-speed OP AMP to provide excellent response to the load transients, and can deliver 1.5A continuous current and transient peaks up to 3A in the...
UR5596 Key Features
- Source and sink current
- Low output voltage offset
- No external resistors required
- Linear topology
- Suspend To Ram (STR) functionality
- Low external ponent count
- Thermal shutdown protection
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