Datasheet4U Logo Datasheet4U.com

U74HC377 - OCTAL D-TYPE FLIP-FLOPS

Datasheet Summary

Description

The device is positive-edge-triggered octal D-type flip-flops with an enable input.

edge of the clock (CLK) pulse, if EN is low.

Features

  • S.
  • Wide Operating Voltage Range of 2V to 6V.
  • Outputs Can Drive Up To 10 LSTTL Loads.
  • Low Power Consumption, ICC=8μA (Max. ).
  • Typical tPD=12ns.
  • ±4mA Output Drive at 5V.
  • Low Input Current of 1μA Max.
  • Eight Flip-Flops With Single-Rail Outputs.
  • Clock Enable Latched to Avoid False Clocking.

📥 Download Datasheet

Datasheet preview – U74HC377

Datasheet Details

Part number U74HC377
Manufacturer Unisonic Technologies
File Size 256.65 KB
Description OCTAL D-TYPE FLIP-FLOPS
Datasheet download datasheet U74HC377 Datasheet
Additional preview pages of the U74HC377 datasheet.

📁 Similar Datasheet

  • U74HC32 - QUADRUPLE 2-INPUT POSITIVE-OR GATES (UTC)
  • U74HC00 - QUADRUPLE 2-INPUT POSITIVE-NAND GATES (UTC)
  • U74HC123 - DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATOR (UTC)
  • U74HC138 - 3-TO-8 LINE DECODERS / DEMULTIPLEXERS (UTC)
  • U74HC14 - HIGH-SPEED CMOS LOGIC HEX INVERTING SCHMITT TRIGGER (UTC)
  • U74HC148 - 8-LINE TO 3-LINE PRIORITY ENCODERS (UTC)
  • U74HC164 - 8-BIT SERIAL-IN AND PARALLEL-OUT SHIFT REGISTER (UTC)
  • U74HC165 - 8-BIT PARALLEL-LOAD SHIFT REGISTER (UTC)
  • U74HC1G06 - SINGLE INVERTER (UTC)
  • U74HC1G66 - BILATERAL SWITCH (UTC)
Other Datasheets by Unisonic Technologies
  • U74HC373 - OCTAL D-TYPE TRANSPARENT LATCH
  • U74HC374 - OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
  • U74HC02 - HCQUADRUPLE 2-INPUT NOR GATES
  • U74HC04 - HEX INVERTERS
  • U74HC07 - HEX INVERTERS
  • U74HC08 - QUAD 2-INPUT AND GATES
  • U74HC157 - QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS / MULTIPLEXERS
  • U74HC20 - DUAL 4-INPUT NAND GATES

Full PDF Text Transcription

Click to expand full text
UNISONIC TECHNOLOGIES CO., LTD U74HC377 OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE  DESCRIPTION The device is positive-edge-triggered octal D-type flip-flops with an enable input. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse, if EN is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. These devices are designed to prevent false clocking by transitions at EN .  FEATURES * Wide Operating Voltage Range of 2V to 6V * Outputs Can Drive Up To 10 LSTTL Loads * Low Power Consumption, ICC=8μA (Max.
Published: |