U74HC377 Description
The device is positive-edge-triggered octal D-type flip-flops with an enable input. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse, if EN is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse.
U74HC377 Key Features
- Wide Operating Voltage Range of 2V to 6V
- Outputs Can Drive Up To 10 LSTTL Loads
- Low Power Consumption, ICC=8μA (Max.)
- Typical tPD=12ns
- ±4mA Output Drive at 5V
- Low Input Current of 1μA Max
- Eight Flip-Flops With Single-Rail Outputs
- Clock Enable Latched to Avoid False Clocking