SI7136DP Datasheet | Vaishali Semiconductor

.. SPICE Device Model Si7136DP Vishay Siliconix N-Channel 20-V (D-S) MOSFET CHARACTERISTICS - N-Channel Vertical DMOS - Macro Model (Subcircuit Model) - Level 3 MOS - Apply for both Linear and Switching Application - Accurate over the - 55 to 125°C Temperature Range - Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the - 55 to 125°C temperature ranges under the pulsed 0-V to 10-V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a mercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 74158 S-60180Rev. A, 13-Feb-06 .vishay. 1 SPICE Device Model Si7136DP Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Current a Symbol Test Condition Simulated Data 1.8 1671 0.0026 0.0036 23 0.76 Measured Data Unit VGS(th) ID(on) r DS(on) gfs VSD VDS = VGS, ID = 250 µA VDS ≥ 5 V, VGS = 10 V VGS = 10 V, ID = 20 A VGS = 4.5 V, ID = 17 A VDS = 15 V, ID = 20 A IS = 2.7 A V A 0.0026 0.0036 92 0.72 Ω S V Drain-Source On-State Resistancea Forward Transconductancea Diode Forward Voltagea Dynamicb Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Gate-Source Charge...