VS3V257 Datasheet | Vaishali Semiconductor

Description The VS3V257 is a high-speed LVTTL- patible Quad 2:1 multiplexer/demultiplexer. The VS3V257 contains four mux/demux channels, with a mon path control (S) and active low enable (/E). The low ON resistance of the VS3V257 allows inputs to be connected to outputs, without adding propagation delay and without generating additional signal noise. The VS3V2257 has 25Ω resistors in series with the switches to reduce ground-bounce noise and signal reflection. The VS3V257 and VS3V2257 are designed for 3.3V to 2.5V or 2.5V to 1.8V level translation, without any external ponents. These switches also offer very high impedance between switch terminals in the power-off or “disabled” state. This feature , bined with near-zero propagation delay in the “on” state, makes VS3V257 and VS3V2257 ideal interface elements for hot-swapping applications. Features - = - = Enhanced N-FET with no DC path to VCC or GND in normal operating signal voltage range. Low impedance switches connect inputs to outputs with near-zero propagation delay: 5Ω (VS3V257) and 25Ω (VS3V2257) Pin-patible with 74LVC257 or equivalent logic devices Zero added ground bounce or signal noise - = - = - = - = - = - = Break-before-make feature Undershoot clamp diodes on all switch and control pins ESD rating >2000V (Human Body Model) or >200V (Machine Model) Latch-up current >100m A Available in 150-mil wide QSOP package - = - = Figure 1. Functional Block Diagram Figure 2. Pin Configuration S /E YA YB YC YD I0A I1A I0B I1B I0C I1C I0D I1D S I0A I1A YA I0B I1B YB GND 1 2 3 4 5 6 7 8 QSOP 16 15 14 13 12 11 10 9 VCC /E I0D I1D YD I0C I1C YC (All Pins Top View) 2000-11-28 Vaishali Semiconductor Page 1 .vaishali. 747 Camden Avenue, Suite C Campbell CA 95008 MDSS-0001-01 Ph. 408.377.6060 Fax 408.377.6063 VS3V257/VS3V2257 Table 1. Pin Description Name I/O Description I0X, I1X S /E YA - YD I/O I I I/O Data Input or Output Select Input Enable Input Data Output or Input Table 2. Function Table Inputs Path /E H L L S X L H Hi...