VT83027 Datasheet | Vaishali Semiconductor

Description The Vaishali VT83027 is a single-chip, integrated VCXO and Phase Locked Loop (PLL) clock synthesizer. The device uses the VCXO and an analog Phase-Locked Loop (PLL) to accept a 13.5 MHz, 14 p F (pull range of 200 ppm) crystal input, and produce a 27 MHz output. A 0 to 3V control signal is used to fine tune the output clock frequency in the ±100ppm range. Features - = - = - = 3.3V supply operation Low jitter PLL Clock Synthesizer - = Zero ppm synthesis error Uses inexpensive pullable crystal - = - = - = ±12m A drive capability On-chip oscillator with 200 ppm pull range (±100 ppm) 8 pin SOIC package Figure 1. Functional Block Diagram Figure 2. Pin Configuration VDD1 VDD2 VIN X2 13.5 MHz Pullable Crystal Load Cap Control Low Phase osc Noise PLL X1 VDD1 Output Buffer CLK1 1 2 3 4 8 7 6 5 X2 GND1 VDD2 CLK Load Caps VIN GND2 8 pin (150 mil) SOIC X1 GND1 GND2 2001-04-17 Vaishali Semiconductor Page 1 .vaishali. 747 Camden Avenue, Suite C Campbell CA 95008 MDST-0003-03 Ph. 408.377.6060 Fax 408.377.6063 Table 1. Pin Description Name X1 VDD1 VIN GND2 CLK VDD2 GND1 X2 1 2 3 4 5 6 7 8 Pin # Type Xi P I P O P P Xi Core VDD. Connect to 3.3V Description Crystal connection. Connect to a 13.5 MHz pullable crystal Voltage input to VCXO. Zero to 3V signal controls the frequency of the VCXO. Connect to ground. Clock output Output driver VDD . Connect to 3.3V Connect to ground. Crystal connection. Connect to a13.5 MHz pullable crystal. Legend: I = Input O = Output P = Power supply connection Xi = Crystal connections. Table 2. Pullable Crystal Specifications...