VG36128801BT Overview
16 x 4 (word x bit x bank), respectively. All input and outputs are synchronized with the positive edge of the clock.The synchronous DRAMs are patible with Low Voltage TTL (LVTTL).These products are packaged in 54-pin TSOPII.
VG36128801BT Key Features
- Single 3.3V ( ± 0.3V ) power supply
- High speed clock cycle time -7H: 133MHz<2-2-2>, -7L: 133MHz<3-3-3>, -8H: 100MHz<2-2-2>
- Fully synchronous operation referenced to clock rising edge
- Possible to assert random column access in every cycle
- Quad internal banks controlled by BA0 & BA1 (Bank Select)
- Byte control by LDQM and UDQM for VG36128161DT
- Programmable Wrap sequence (Sequential / Interleave)
- Programmable burst length (1, 2, 4, 8 and full page)
- Programmable /CAS latency (2 and 3)
- Automatic precharge and controlled precharge