VG36128801BT
Description
x 4 (word x bit x bank), respectively. VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM The VG36128401B, VG36128801B and VG3664128161B are high-speed 134,217,728-bit synchronous dynamic random-access memories, organized as 8,388,608 x 4 x 4, 4,194,304 x 8 x 4 and 2,097,152 x The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.
Key Features
- Single 3.3V ( ± 0.3V ) power supply
- High speed clock cycle time -7H: 133MHz<2-2-2>, -7L: 133MHz<3-3-3>, -8H: 100MHz<2-2-2>
- Fully synchronous operation referenced to clock rising edge
- Possible to assert random column access in every cycle
- Quad internal banks controlled by BA0 & BA1 (Bank Select)
- Byte control by LDQM and UDQM for VG36128161DT
- Programmable Wrap sequence (Sequential / Interleave)
- Programmable burst length (1, 2, 4, 8 and full page)
- Programmable /CAS latency (2 and 3)
- Automatic precharge and controlled precharge
