VG37648041AT Datasheet | Vanguard International Semiconductor

Description Preliminary VG37648041AT 256M:x4, x8, x16 CMOS Synchronous Dynamic RAM The 256Mb DDR SDRAM is a high-speed S, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM. The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 256Mb DDR SDRAM effectively consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cyc...