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VG37648041AT - 256M:x4/ x8/ x16 CMOS Synchronous Dynamic RAM

General Description

The 256Mb DDR SDRAM is a high-speed COMS, dynamic random-access memory containing 268,435,456 bits.

It is internally configured as a quad-bank DRAM.

Key Features

  • and functionality required for JEDEC DDR devices; options not required but listed, are noted as such. Certain vendors may elect to offer a superset of this specification by offering improved timing and/or including optional features. Users benefit from knowing that any system design based on the required aspects of this specification are supported by all DDR SDRAM vendors; conversely, users seeking to use any superset specifications bear the responsibility to verify support with individual vendo.

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Datasheet Details

Part number VG37648041AT
Manufacturer Vanguard International Semiconductor
File Size 966.77 KB
Description 256M:x4/ x8/ x16 CMOS Synchronous Dynamic RAM
Datasheet download datasheet VG37648041AT Datasheet

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Full PDF Text Transcription (Reference)

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VIS Description Preliminary VG37648041AT 256M:x4, x8, x16 CMOS Synchronous Dynamic RAM The 256Mb DDR SDRAM is a high-speed COMS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM. The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 256Mb DDR SDRAM effectively consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.