SI9936BDY Datasheet | Vishay

DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the - 55 to 125°C temperature ranges under the pulsed 0 to 10V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC Data Shee . . This document is intended as a SPICE modeling guideline and does not constitute a mercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 72573 02-Jun-04 .vishay. . Data Sheet 4 U . .. SPICE Device Model Si9936BDY Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Current a Symbol Test Conditions Simulated Data 1.9 165 0.027 0.038 13 0.80 Measured Data Unit VGS(th) ID(on) r DS(on) gfs VSD VDS = VGS, ID = 250 µA VDS ≥ 5 V, VGS = 10 V VGS = 10 V, ID = 6 A VGS = 4.5 V, ID = 4.9 A VDS = 15 V, ID = 6 A IS = 1.7 A, VGS = 0 V V A 0.028 0.041 12 0.80 Ω S V Drain-Source On-State Resistancea Forward Transconductancea Forward Voltagea Dynamicb Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Qg Qgs Qgd td(on) tr td(off) tf VDD = 15 V, RL = 15 Ω ID ≅ 1 A, VGEN = 10 V, RG = 6 Ω VDS = 15 V, VGS = 10 V, ID = 6 A 8 1.8 1.5 16 8 23 6 8.6 1.8 1.5 10 15 25 10 ns n C et4U. Notes a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%. b. Guaranteed by design, not subject to production testing. Data Shee . . .vishay. Document Number: 72573...