FEATURES
D Two-Chip Design D High Slew Rate D Low Offset/Drift Voltage D Low Gate Leakage: 3 pA D Low Noise: 12 nV⁄√Hz @ 10 Hz D Good CMRR: 76 dB D Minimum Parasitics BENEFITS D Tight Differential Match vs. Current D Improved Op Amp Speed, Settling Time Accuracy D Minimum Input Error/Trimming Requirement D Insignificant Signal Loss/Error Voltage D High System Sensitivity D Minimum Error with Large Input Signals D Maximum High Frequency Performance APPLICATIONS
D Wideband Differential Amps D High-Speed, Temp-Compensated, Single-Ended Input Amps D High-Speed Comparators D Impedance Converters D Matched Switches DESCRIPTION
<5 mV offset between the two die. The hermetically-sealed TO-71 package is available with full military processing (see Military Information). For similar products see the low-noise U/SST401 series, and the low-leakage 2N5196/5197/5198/5199 data sheets. TO-71 S1 1 D1 2 G2 6 5 D2 3 G1 4 S2 Top View ABSOLUTE MAXIMUM RATINGS
Gate-Drain, Gate-Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40 V Gate-Gate Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Vishay
