DM1883A Description
...CI) en IiiThe DM1BB3 Direct Memory Access Controller g(DMAC) is packaged in a 40 pin standard dual in- ::::l line package. The chip requires a single +5 power «supply input and a single clock input. The device contains B CPU addressable registers, and allows for up to 8 CPU addressable device registers if the automatic device chip select.
DM1883A Key Features
- SINGLE +5 VDC POWER SUPPLY o B BIT BI-DIRECTIONAL DATA BUS o TRUE OR PLEMENT DATA BUS
- B CPU ADDRESSABLE DMAC REGISTERS
- B CPU ADDRESSABLE DEVICE REGISTERS
- AUTOMATIC GENERATION OF DEVICE CS
- 256K MEMORY ADDRESSING o 64K PROGRAMMABLE PAGE PROTECTION o BYTE OR WORD DMA TRANSFERS o INTERRUPT AND BUS REQUEST CAPAB
- STOP REQUEST INPUT TO DELAY INTERRUPT OR BUS REQUESTS
- B BIT PROGRAMMABLE INTERRUPT IDCODE