EDI88128CS Description
I/O0-7 Data Inputs/Outputs A0-16 Address Inputs WE# Write Enable CS# Chip Select OE# Output Enable VCC Power (+5V ±10%) VSS Ground NC Not Connected BLOCK DIAGRAM Memory Array Address Buffer Address Decoder I/O Circuits I/O0-7 WE# CS# OE# White Electronic Designs Corp. reserves the right to change products or specifications without notice. 10 1 White Electronic Designs Corporation (602) 437-1520 .whiteedc.
EDI88128CS Key Features
- Access Times of 15-, 17, 20, 25, 35, 45, 55ns
- CS# and OE# Functions for Bus Control
- 2V Data Retention (EDI88128LPS)
- TTL patible Inputs and Outputs
- Fully Static, No Clocks
- 32 pad Ceramic LCC (Package 141)
- 32 lead Ceramic Flatpack (Package 142)
- Single +5V (±10%) Supply OperationThe EDI88128CS is a high speed, high performance, 128Kx8 megabit density Monolithic CM
- Organized as 128Kx8
- mercial, Industrial and Military Temperature