WED3EG7218S-JD3 Datasheet | White Electronic Designs

ATURES Double-data-rate architecture DDR200, DDR266, DDR333 and DDR400 - JEDEC design specified BI-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input. Auto and self refresh Serial presence detect Power supply: - VCC = VCCQ = 2.5V±0.2V (100, 133 and 166MHz) - VCC = VCCQ = 2.6V±0.1V (200MHz) - This product is under development, is not qualified or characterized and is subject to change without notice. DESCRIPTION The WED3EG7218S is a 16Mx72 Double Data Rate SDRAM memory module based on 128Mb DDR SDRAM ponent. The module consists of nine 16Mx8 DDR SDRAMs in 66 pin TSOP packages mounted on a 184 pin FR4 substrate. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. JEDEC 184 pin DIMM package - JD3 PCB height: 30.48 (1.20") Max NOTE: Consult factory for availability of: - Ro HS Products - Vendor source control options - Industrial temperature option OPERATING FREQUENCIES DDR400 @CL=3 Clock Speed CL-t RCD-t RP 200MHz 3-3-3 DDR333 @CL=2.5 166MHz 2.5-3-3 DDR266 @CL=2 133MHz 2-2-2 DDR266 @CL=2.5 133MHz 2.5-3-3 DDR200 @CL=2 100MHz 2-2-2 June 2006 Rev. 2 White Electronic Designs Corporation - (602) 437-1520 - .wedc. .. White Electronic Designs A0 - A12 BA0-BA1 DQ0-DQ63 CB0-CB7 DQS0-DQS8 CK0, CK1, CK2 CK0#, CK1#, CK2# CKE0 CS0# RAS# CAS# WE# DQM0-DQM8 VCC VCCQ VSS VREF VCCSPD SDA SCL SA0-SA2 VDDID NC PRELIMINARY PIN CONFIGURATION Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Front VREF DQ0 VSS DQ1 DQS0 DQ2 VCC DQ3 NC NC VSS DQ8 DQ9 DQS1 VCCQ CK1 CK1# VSS DQ10 DQ11 CKE0 VCCQ...