W3EG72125S-JD3 - 1GB - 2x64Mx72 DDR SDRAM REGISTERED ECC

This page provides the datasheet information for the W3EG72125S-JD3, a member of the W3EG72125S-AJD3 1GB - 2x64Mx72 DDR SDRAM REGISTERED ECC family.

Description

The W3EG72125S is a 2x64Mx72 Double Data Rate SDRAM memory module based on 256Mb DDR SDRAM components.

The module consists of eighteen 2x64Mx4 stacked (36 components), in 66 pin TSOP package mounted on a 184 pin FR4 substrate.

Features

Double-data-rate architecture Clock Speeds of 100MHz, 133MHz and 166MHz Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh Serial presence detect Dual Rank Power supply: VCC = 2.5V ± 0.2V JEDEC standard 184 pin DIMM package.
Package height options: www. DataSheet4U. com JD3:.

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Datasheet Details

Part number	W3EG72125S-JD3
Manufacturer	White Electronic
File Size	402.03 KB
Description	1GB - 2x64Mx72 DDR SDRAM REGISTERED ECC
Datasheet	W3EG72125S-JD3 Datasheet
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Full PDF Text Transcription

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White Electronic Designs W3EG72125S-D3 -JD3 -AJD3 PRELIMINARY* 1GB – 2x64Mx72 DDR SDRAM REGISTERED ECC w/PLL FEATURES Double-data-rate architecture Clock Speeds of 100MHz, 133MHz and 166MHz Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh Serial presence detect Dual Rank Power supply: VCC = 2.5V ± 0.2V JEDEC standard 184 pin DIMM package • Package height options: www.DataSheet4U.com JD3: 30.48mm (1.20") and AJD3: 28.70mm (1.

Published: Jun 8, 2007 |