W3EG72126S-AJD3 - 1GB-128Mx72 DDR SDRAM REGISTERED ECC

Description

The W3EG72126S is a 128Mx72 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM components.

The module consists of eighteen 128Mx4 DDR SDRAMs in 66 pin TSOP packages mounted on a 184 pin FR4 substrate.

Synchronous design allows precise cycle control with the use of system clock.

Features

Double-data-rate architecture DDR200, DDR266 and DDR333:.
JEDEC design speciﬁcations Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input. Auto and self refresh Serial presence detect Power supply: VCC = 2.5V ± 0.20V JEDEC standard 184 pin DIMM package www. DataSheet4U. com.

White Electronic

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Datasheet Details

Part number	W3EG72126S-AJD3
Manufacturer	White Electronic
File Size	364.66 KB
Description	1GB-128Mx72 DDR SDRAM REGISTERED ECC
Datasheet	W3EG72126S-AJD3 Datasheet
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White Electronic Designs W3EG72126S-D3 -JD3 -AJD3 PRELIMINARY* 1GB-128Mx72 DDR SDRAM REGISTERED ECC w/PLL FEATURES Double-data-rate architecture DDR200, DDR266 and DDR333: • JEDEC design speciﬁcations Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input. Auto and self refresh Serial presence detect Power supply: VCC = 2.5V ± 0.20V JEDEC standard 184 pin DIMM package www.DataSheet4U.com DESCRIPTION The W3EG72126S is a 128Mx72 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM components.

Published: Jun 8, 2007 |