W3EG72255S-JD3 Key Features
- JEDEC design specifications Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Late
| Part Number | Description |
|---|---|
| W3EG72255S-AJD3 | 2GB - 2x128Mx72 DDR SDRAM REGISTERED ECC |
| W3EG72255S-D3 | 2GB - 2x128Mx72 DDR SDRAM REGISTERED ECC |
| W3EG72256S-AJD3 | 2GB-256Mx72 DDR SDRAM REGISTERED ECC |
| W3EG72256S-JD3 | 2GB-256Mx72 DDR SDRAM REGISTERED ECC |
| W3EG72125S-AJD3 | 1GB - 2x64Mx72 DDR SDRAM REGISTERED ECC |