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W3EG72255S-JD3 - 2GB - 2x128Mx72 DDR SDRAM REGISTERED ECC

This page provides the datasheet information for the W3EG72255S-JD3, a member of the W3EG72255S-AJD3 2GB - 2x128Mx72 DDR SDRAM REGISTERED ECC family.

Description

The W3EG72255S is a 2x128Mx72 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM components.

The module consists of eighteen 256Mx4 stacks, in 66 pin TSOP packages mounted on a 184 pin FR4 substrate.

Synchronous design allows precise cycle control with the use of system clock.

Features

  • Double-data-rate architecture DDR200, DDR266 and DDR333:.
  • JEDEC design specifications Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input. Auto and self refresh Serial presence detect Dual Rank Power supply: VCC = 2.5V ± 0.2V www. DataSheet4U. com.

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Datasheet Details

Part number W3EG72255S-JD3
Manufacturer White Electronic
File Size 273.68 KB
Description 2GB - 2x128Mx72 DDR SDRAM REGISTERED ECC
Datasheet download datasheet W3EG72255S-JD3 Datasheet
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White Electronic Designs W3EG72255S-D3 -JD3 -AJD3 PRELIMINARY* 2GB – 2x128Mx72 DDR SDRAM REGISTERED ECC, w/PLL FEATURES Double-data-rate architecture DDR200, DDR266 and DDR333: • JEDEC design specifications Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input. Auto and self refresh Serial presence detect Dual Rank Power supply: VCC = 2.5V ± 0.2V www.DataSheet4U.com DESCRIPTION The W3EG72255S is a 2x128Mx72 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM components. The module consists of eighteen 256Mx4 stacks, in 66 pin TSOP packages mounted on a 184 pin FR4 substrate.
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