W83L177R Datasheet | Winbond

DESCRIPTION The W83L177R is a 10 outputs SDRAM clock buffer for 2-DIMMs models incorporate with W83L197R-16 which is the clock synthesizer especially for the 100MHz models such as Intel BX chipsets.(Refer the datasheet fo Winbond W83L197R-16) The W83L177R receives the clock from chipset by the Buffer_In pin and provides almost zerodelay (less than 4ns propagation delay) SDRAM buffer outputs for the 10 SDRAM clocks which are synchronous with the CPU clock outputs priovided by W83L197R-16. The clock skew between any two clock outputs is less than 250ps and the output buffer impedance is about 15 ohms. The W83L177R also provides I2C serial bus interface to program the registers to enable or disable each SDRAM clock outputs. 2.0 PRODUCT FEATURES - Supports Intel Pentium II CPUs for BX chipset - 10 SDRAM clocks for 2-DIMMs - Clock skew less than 250ps - Almost none delay Buffer-in controlling SDRAM clocks(< 4ns propagation delay) - I2C 2-wire serial interface - Programmable registers to enable/stop each output - Incorporate with W83L197R-16 - 28pin-SOP package (209mil) -2- Publication Release Date: Mar. 1999 Revision 1.0 3.0 BLOCK DIAGRAM SDATA SCLK Serial port device Control OE SDRAM0 SDRAM1 SDRAM2 SDRAM3 SDRAM4 SDRAM5 SDRAM6 SDRAM7 Buffer_In SDRAM8 SDRAM9 4.0 PIN CONFIGURATION Vdd SDRAM 0 SDRAM 1 Vss Vdd SDRAM 2 SDRAM 3 Vss BUFFER_IN Vdd SDRAM 8 Vss Vdd IIC - SDATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vdd SDRAM7 SDRAM6 Vss Vdd SDRAM 5 SDRAM 4 Vss - OE Vdd SDRAM 9 Vss Vss IIC - SCLOCK -3- Publication Release Date: Mar. 1999 Revision 1.0 5.0 PIN DESCRIPTION - Input OUT - Output I/O - Bi-directional Pin - - Internal 250kΩ pull-up SYMBOL SDRAM [ 0:9] - SDATA - SDCLK - OE BUFFER_IN VDDIIC VSSIIC Vdd Vss PIN 2,3,6,7,11,18, 22,23,26,27 14 15 20 9 13 16 I/O FUNCTION O SDRAM clock outputs which have the same frequency as CPU clocks. I/O Serial data of I2C 2-wire control interface IN Serial clock of I2C 2-wire...