W83L177R Description
The clock skew between any two clock outputs is less than 250ps and the output buffer impedance is about 15 ohms. The W83L177R also provides I2C serial bus interface to program the registers to enable or disable each SDRAM clock outputs.
W83L177R Key Features
- Supports Intel Pentium II CPUs for BX chipset
- 10 SDRAM clocks for 2-DIMMs
- Clock skew less than 250ps
- Almost none delay Buffer-in controlling SDRAM clocks(< 4ns propagation delay)
- I2C 2-wire serial interface
- Programmable registers to enable/stop each output
- Incorporate with W83L197R-16
- 28pin-SOP package (209mil)