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W946432AD - DDR SDRAM

Datasheet Summary

Description

The W946432AD is a high-speed CMOS Double Data Rate synchronous dynamic random access memory organized as 512K words x 4 banks x 32 bits.

A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver.

Features

  • Double-data-rate architecture; two data transfers.
  • Four.
  • Data.
  • Burst.
  • CAS internal banks for concurrent operation mask (DM) for write data lengths: 2, 4, or 8 Latency: 3 per clock cycle.
  • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver is edge-aligned with data for READs; center-aligned with data for WRITEs clock inputs (CLK and CLK ).
  • DQS.
  • AUTO.
  • Auto.

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Datasheet Details

Part number W946432AD
Manufacturer Winbond
File Size 480.12 KB
Description DDR SDRAM
Datasheet download datasheet W946432AD Datasheet
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www.DataSheet4U.com W946432AD 512K × 4 BANKS × 32 BITS DDR SDRAM GENERAL DESCRIPTION The W946432AD is a high-speed CMOS Double Data Rate synchronous dynamic random access memory organized as 512K words x 4 banks x 32 bits. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The W946432AD operates from a differential clock (CLK and CLK the crossing of CLK going HIGH and CLK going LOW will be referred to as the postive edge of CLK). Commands (address and control signals) are registered at every positive edge of CLK.
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