XM28C040P Datasheet | Xicor Inc.

FEATURES - High Density Memory Module - 150ns, 200ns, and 250ns Access Times Available - 4 Megabit Memory in 1 square inch. - Flexible Multiplane Architecture - Four Separate Chip Selects - 32 Separate I/Os - User Configurable I/Os- x8, x16, or x32 - User Configurable Page Size- 64 Doublewords, 128 Words, or 256 Bytes - Concurrent Read/Write Operations - Able to Continue Reading During a Nonvolatile Write Cycle. - 5 Volt Byte or Page Alterable - No Erase Before Write - Software Data Protection - Early End of Write Polling - DATA Polling - Toggle Bit Polling - High Reliability - Endurance: 100,000 Cycles - Data Retention: 100 Years FUNCTIONAL DIAGRAM OE WE1 CE1 WE2 CE2 WE3 CE3 WE4 CE4 DESCRIPTION The XM28C040P is a high density CMOS byte alterable nonvolatile memory array constructed on a cofired ceramic substrate using Xicor’s 128K x 8 ponents in 32-pad leadless chip carriers. The Substrate is a 66-pin ceramic pin grid array. The module is configured with four separate chip enable and write enable inputs and 32 separate I/Os. This, along with the small footprint, provides the end user with a large degree of flexibility in board layout and memory configuration. In addition, with the large number of pins and the growth path being implemented, the module will be able to grow to 16 megabits. 128K x 8 128K x 8 128K x 8 128K x 8 A0-A16 I/O0-I/O7 I/O8-I/O15 I/O16-I/O23 I/O24-I/O31 ©Xicor, 1995, 1996 Patents Pending 7053 8/13/97 T0/C0/D0 SH Characteristics subject to change without notice PIN CONFIGURATION 1 12 23 34 45 56 I/O8 WE2 CE2 I/O9 A10 I/O14 I/O22 VCC CE4 I/O23 A10 I/O28 I/O24 WE4 I/O27 A7 A12 I/O25 I/O26 A4 A1 A2 A3...