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17S50A - Spartan-II/Spartan-IIE Family OTP Configuration PROMs

This page provides the datasheet information for the 17S50A, a member of the 17S15APC Spartan-II/Spartan-IIE Family OTP Configuration PROMs family.

Description

Pin Description Data output, High-Z state when either CE or OE are inactive.

During programming, the DATA pin is I/O.

Features

  • Configuration one-time programmable (OTP) read-only memory designed to store configuration bitstreams for Spartan-II/Spartan-IIE FPGA devices.
  • Simple interface to the Spartan device.
  • Programmable reset polarity (active High or active Low).
  • Low-power CMOS floating gate process www. DataSheet4U. com.
  • 3.3V PROM.
  • Available in compact plastic 8-pin DIP, 8-pin VOIC, 20-pin SOIC, or 44-pin VQFP packages. Programming supp.

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Datasheet preview – 17S50A

Datasheet Details

Part number 17S50A
Manufacturer Xilinx
File Size 119.59 KB
Description Spartan-II/Spartan-IIE Family OTP Configuration PROMs
Datasheet download datasheet 17S50A Datasheet
Additional preview pages of the 17S50A datasheet.

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0 R Spartan-II/Spartan-IIE Family OTP Configuration PROMs (XC17S00A) 5 DS078 (v1.8) November 18, 2002 0 Advance Product Specification Features Configuration one-time programmable (OTP) read-only memory designed to store configuration bitstreams for Spartan-II/Spartan-IIE FPGA devices • Simple interface to the Spartan device • Programmable reset polarity (active High or active Low) • Low-power CMOS floating gate process www.DataSheet4U.com • 3.3V PROM • • • • • Available in compact plastic 8-pin DIP, 8-pin VOIC, 20-pin SOIC, or 44-pin VQFP packages. Programming support by leading programmer manufacturers. Design support using the Xilinx Alliance and Foundation series software packages.
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